ADF4378 datasheet(41/84 Pages) AD

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Data Sheet

ADF4378

APPLICATIONS INFORMATION

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Rev. A | 41 of 84

The method provided in the Fast Power-Up and Initialization, Man-

ually Programmed VCO Calibration Settings (Optional) section is an

optional power-up procedure after the initial power-up.

Standard Power-Up and Initialization

Sequence, Automatic VCO Calibration

The following standard power-up and initialization sequence is the

recommended procedure to power up and program the ADF4378:

1. Follow Step 1 through Step 5 in the Power-Up and Initialization

Sequence section, using the register settings provided in the

Design Procedure section.

2. It is optional to monitor the status of the VCO calibration bit

fields, ADC_BUSY, and FSM_BUSY. A VCO calibration is com-

pleted when ADC_BUSY transitions from high to low, followed

by FSM_BUSY transitioning from high to low. Typical automatic

VCO calibration times range from 3 ms to 9 ms.

3. After the VCO calibration completes, disable the VCO cal-

ibration clocks by setting EN_DRCLK = EN_DNCLK =

EN_ADC_CLK = 0. Disabling the VCO calibration clocks re-

duces the V3.3V_1 current by roughly 15 mA and reduces

unwanted spurious content.

4. PLL is locked when the lock detector sets the LKDET pin and

the LOCKED bit high.

Fast Power-Up and Initialization, Manually

Programmed VCO Calibration Settings

(Optional)

The purpose of the fast power-up and initialization method is to

avoid the automatic VCO calibration time, which is typically 3 ms to

9 ms. For fixed clock frequency converter applications, such as this

design and programming Example 1, automatic VCO calibration

times are typically acceptable. The following list provides the steps

to record the VCO calibration results on the initial power-up and

manually program VCO Calibration settings on subsequent power

ups:

►

On initial power, follow the procedure shown in the Standard

Power-Up and Initialization Sequence, Automatic VCO Calibra-

tion section.

►

Record calibration results from the VCO_CORE, VCO_BAND,

and VCO_BIAS bit fields and store the recorded results in mem-

ory. Note that each unique device and frequency combination

generates different VCO_CORE, VCO_BAND, and VCO_BIAS

values.

►

Subsequent power-up and initialization sequences (for more

information, see the Power-Up and Initialization Sequence sec-

tion) can bypass the automatic VCO calibration procedure by

programming the override (O_VCO_CORE, O_VCO_BAND, and

O_VCO_BIAS) and manual (M_VCO_CORE, M_VCO_BAND,

and M_VCO_BIAS) VCO register bits with the register settings

provided in Table 37. All other bit fields from the Design Proce-

dure section remain the same.

Table 37. Manually Programmed VCO Calibration Settings

Bit Fields

Value

EN_AUTOCAL

0x0

EN_DRCLK

0x0

EN_DNCLK

0x0

EN_ADC_CLK

0x0

O_VCO_CORE

0x1

O_VCO_BAND

0x1

O_VCO_BIAS

0x1

M_VCO_CORE

Program M_VCO_CORE, M_VCO_BAND, and

M_VCO_BIAS with recorded VCO_CORE,

VCO_BAND, and VCO_BIAS values, respectively,

from the Standard Power-Up and Initialization

Sequence, Automatic VCO Calibration section

M_VCO_BAND

M_VCO_BIAS

ALIGNING MULTIPLE ADF4378 OUTPUT

PHASES

Aligning multiple ADF4378 output phases break into two steps. The

first step ensures that the reference dividers, reference doubler, and

clock output divider of the multiple devices are setup correctly to

ensure phase alignment. The second step minimizes output-to-out-

put skew between multiple ADF4378 devices.

Step 1: Phase Alignment

The ADF4378 architecture includes the clock output divider and the

output invert inside the integer PLL feedback loop (see Functional

Block Diagram), which allows the locked PLL to align the clock

output divider phase to the reference input phase. Therefore, to

align multiple ADF4378 output phases, ensure that the reference

phases are aligned at all the reference input pins of the ADF4378.

Because the reference divider and reference doubler are outside of

the PLL loop, see Table 38 to ensure that phase alignment between

multiple ADF4378 devices is guaranteed.

Table 38. Reference Settings to Align Multiple ADF4378 Devices

Reference Divider and

Doubler State

Guaranteed Reference to Output Phase Alignment

EN_RDBLR = 1

Yes

R_DIV = 1

Yes

R_DIV > 1

When fOUT/fREF = integer, and fREF ≤ fOUT

Step 2: Output-to-Output Skew Adjustment

Any variation in reference input to output propagation delay (tPD)

between multiple ADF4378 devices presents itself as output skew

between multiple ADF4378 devices.

To minimize tPD across process and temperature, select the DMA

of the reference input buffer by setting REF_SEL = 0. When the

DMA is selected, the typical tPD standard deviation due to process

variation is 3 ps with a temperature coefficient (tPD-TC) of 0.03

ps/°C, as shown in Figure 26 and Figure 22, respectively.

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