ADF4378 datasheet(34/84 Pages) AD

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Data Sheet

ADF4378

APPLICATIONS INFORMATION

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Rev. A | 34 of 84

LOOP FILTER DESIGN

A stable loop filter design requires care in selecting the loop filter

components of the ADF4378. It is recommended to download and

install ADIsimPLL™ for loop filter design and simulation. ADIsimPLL

has an integrated tutorial for first time users and a help manual for

more complex topics. There are also several ADIsimPLL training

videos available on www.analog.com. After a loop filter has been

designed and simulated, it is recommended to verify the new loop

filter using the ADF4378 evaluation hardware.

A full loop filter design tutorial is beyond the scope of this data

sheet. However, some best practices are shown in the following list.

ADIsimPLL aids in defining and simulating these parameters. Any

significant change to these items requires a new loop filter design.

1. A stable loop filter must meet the following criteria:

a. Loop filter phase margin > 45°

b. Loop filter bandwidth < fPFD ÷ 10

2. The required loop filter bandwidth is determined by the following

features of the ADF4378:

a. ICP

b. KVCO

c. PFD frequency

d. Reference input phase noise (for more information, see the

Reference Phase Noise section).

e. Trade-off between minimizing jitter or settling time (for more

information, see the Output Phase Noise Characteristics

section and Equation 12, respectively).

The VTUNE pin has an internal 30 pf capacitor to GND that must

be included in the loop filter design. ADIsimPLL takes this internal

capacitance into account automatically.

REFERENCE SOURCE CONSIDERATIONS

Reference Input Network

The reference input buffer of the ADF4378, shown in Figure 65,

provides a flexible interface to either differential or single-ended

frequency sources. Figure 85 to Figure 90 show recommended

interfaces for different reference signal types. All ZO signal traces

are 50 Ω transmission lines in Figure 85, Figure 86, Figure 87,

Figure 88, Figure 89, and Figure 90.

Figure 85. Single-Ended 50 Ω Source (VREF < 2.6 Vp-p)

Figure 86. Single-Ended 50 Ω Source (VREF > 2.6 Vp-p)

Figure 87. Single-Ended CMOS

Figure 88. Differential LVPECL

Figure 89. Differential LVDS

Figure 90. Differential CML

SYSREF Input Network

The ADF4378’s SYSREF input may be programmed for CML/

LVPECL or LVDS interfaces using the SR_SEL bit to support a

range of input SYSREF signal levels. Figure 91 to Figure 94 show

the examples of SYSREF input interfaces.

ADF4378 Datasheet(PDF) 34 Page - Analog Devices

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