ADF4378 datasheet(8/84 Pages) AD

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Data Sheet

ADF4378

SPECIFICATIONS

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Rev. A | 8 of 84

Table 1. Specifications (Continued)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

12 kHz to 20 MHz Integration

17.7

fsRMS

100 Hz to 100 MHz Integration

18.3

fsRMS

Equivalent ADC SNR Method8

fsRMS

3 GHz Output Frequency

Device setup7, fOUT = 3 GHz

Phase Noise Floor

−165.7

dBc/Hz

RMS Jitter

12 kHz to 20 MHz Integration

17.7

fsRMS

100 Hz to 100 MHz Integration

18.3

fsRMS

Equivalent ADC SNR Method8

fsRMS

1.5 GHz Output Frequency

Device setup7, fOUT = 1.5 GHz

Phase Noise Floor

−169.5

dBc/Hz

RMS Jitter

12 kHz to 20 MHz Integration

19.5

fsRMS

100 Hz to 100 MHz Integration

20.5

fsRMS

Equivalent ADC SNR Method8

fsRMS

Normalized In-Band Phase Noise Floor9

LNORM

−239

dBc/Hz

Normalized 1/f Phase Noise Floor9

L1/f

−287

dBc/Hz

Normalized to 1 Hz

L1/f_1G_10k

−147

dBc/Hz

Normalized to 1 GHz at 10 kHz offset

Spurious

fREF

−105

dBc

LOCKED bit = 1, fREF = 100 MHz, fPFD = 200

MHz, fOUT = 12 GHz

fPFD

−95

dBc

LOCKED bit = 1, fREF = 100 MHz, fPFD = 200

MHz, fOUT = 12 GHz

fSR_IN

−69

dBc

LOCKED bit = 1, fREF = fPFD = 200 MHz, fOUT

= 12 GHz, fSR_IN = 50 MHz

TEMPERATURE SENSOR (ADC)

ADC Clock Frequency

fADC_CLK

400

kHz

ADC clock divider output

ADC Clock Divider Frequency

fADC_CLKDIV

125

MHz

ADC clock divider input

Resolution

Bits

1 1.2 V < VCP < 3.4 V.

2 Valid for 1.60 V ≤ VVTUNE ≤ 2.85 V with device calibrated after a power cycle or software power-on reset.

3 Based on characterization.

4 Device setup: fREF = 200 MHz, fPFD = 200 MHz, fOUT = 3000 MHz, ENCLK = ENSR = CE = High. Bit fields: R_DEL= 0, N_DEL = 0, CP_I = 15, CLKOUT_OP = 1, REF_SEL

= 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1.

5 Device setup: fREF = 250 MHz, fSR_IN = 50 MHz, fOUT = 12750 MHz, ENCLK = ENSR = CE = High. Bit fields: R_DEL= 0, N_DEL = 0, CP_I = 15, CLKOUT_OP = 1,

REF_SEL = 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1.

6 Device setup: fREF = 100 MHz, fPFD = 200 MHz, fOUT = 12.8 GHz, ENCLK = ENSR = CE = High. Bit fields: R_DEL= 0, N_DEL = 0, CP_I = 15, CLKOUT_OP = 1, REF_SEL

= 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1, EN_DNCLK = EN_DRCLK = EN_ADC_CLK = 0, PD_SRMON = 0, PD_SYSREFOUT = 0,

EN_SR = Low.

7 Device setup: fREF = 1000 MHz, fPFD = 500 MHz, ENCLK = ENSR = CE = High. Bit fields: R_DEL = 0, N_DEL_0, CP_I = 15, CLKOUT1_OP = 1, CLKOUT2_OP = 1,

REF_SEL = 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1, the reference oscillator is the 0-CEGM-058AWEL-R-1GHz from NEL Frequency

Control.

8 Phase integration range 1 kHz to fOUT produces the same result as when clocking an ADC.

9 See Equation 18 through Equation 22. These values are modeled in ADIsimPLL™.

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