ADF4378 datasheet(28/84 Pages) AD

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Data Sheet

ADF4378

THEORY OF OPERATION

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Rev. A | 28 of 84

VCO

The VCO core consists of four separate VCOs, each of which uses

256 overlapping bands, which allows the device to cover a wide

frequency range without large VCO sensitivity (KVCO). The output

frequency can be further extended by utilizing the output divider

(see Figure 73).

The correct register values for the VCO_CORE, VCO_BAND, and

VCO_BIAS settings are determined by performing a VCO calibra-

tion. For more information, see the VCO Calibration section. After

a VCO calibration is performed for a specific device and frequen-

cy, the VCO_CORE, VCO_BAND, and VCO_BIAS values can be

recorded. These recorded values may be programmed manually on

subsequent power ups when the same device and frequency are

used, thereby avoiding the VCO calibration time.

Figure 73. VCO and Clock Output Divider

VCO Calibration

A VCO calibration is required to select the correct VCO core, band,

and bias settings for a specific VCO frequency. To perform a VCO

calibration, several registers must be setup as described in this

section. This procedure assumes that the device is powered up, the

required reference frequency is present on the REFP and REFN

pins, and all other registers are programmed correctly. Figure 74

and Figure 75 are provided as visual aids for this procedure.

Figure 74. VCO Calibration Dividers

Figure 75. VCO Calibration Block

To perform a VCO calibration, set up several registers as outlined in

the following procedure:

1. Set register bits based on the RCLK column in Table 22.

2. Set DCLK_DIV1 = 1. Set CAL_CT_SEL, DCLK_DIV2, and

DCLK_MODE to the values given in Table 17. Record fDIV_RCLK

for later use.

3. Calculate and set the minimum values for the

SYNTH_LOCK_TIMEOUT bit fields, Bits[14:0], the

VCO_ALC_TIMEOUT bit fields, Bits[14:0], and the

VCO_BAND_DIV bits. Typical automatic VCO calibration times

are 3 ms to 9 ms when minimum values are chosen for these

parameters. Larger values produce longer VCO calibration

times.

SYNTH_LOCK_TIMEOUT≥Ceiling

200 μs×fDIV_RCLK

(13)

VCO_ALC_TIMEOUT≥Ceiling

50 μs×fDIV_RCLK

(14)

VCO_BAND_DIV≥Ceiling

15 μs×fDIV_RCLK

16×2DCLK_MODE

(15)

4. Ensure that the ADC_CLK_DIV bits are set so that the required

analog-to-digital converter (ADC) clock frequency is <400 kHz.

ADC

_CLK_DIV > Ceiling

fDIV_RCLK

400 kHz −2

(16)

5. Set the N_INT bit fields, Bits[11:0], CLKOUT_DIV bits, R_DIV

bits, and EN_RDBLR bits by programming REG0010 last. Any

write to REG0010 starts the VCO automatic calibration.

6. This is an optional step. Monitor the register bits, ADC_BUSY,

and FSM_BUSY. The calibration is finished when ADC_BUSY

transitions from high to low, followed by FSM_BUSY transition-

ing from high to low.

ADF4378 Datasheet(PDF) 28 Page - Analog Devices

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