TC9328AF datasheet(43/84 Pages) TOSHIBA

43 / 84 page

TC9328AF

2004-09-13

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Phase Comparator and Lock Detection Port

The phase comparator compares the difference in phasing between the reference frequency signal

supplied from the reference frequency divider and frequency division output of the programmable counter

and outputs the result. Then it controls the VCO (Voltage control oscillator) via a low pass filter in order to

ensure that the two frequency signals and the phase difference match.

Two tristate buffer DO1 and DO2 are outputted in parallel from the phase comparator, the filter constant

can be designed for each VHF and AM bands. A charge pump output uses constant voltage Vreg potential

(1.5 V) so that a stabilized phase comparison machine can be used when VDD potential is 0.9 V.

Also DO2 pin can be used with DO2 control port as general-purpose output port and charge pump signal

(P, N) can be outputted from DO1 and DO2 pins. Therefore it is possible to use an external charge pump.

DO1 control Port and the Unlock Detection Port

M0 and M1 bit of DO2 control ports perform a general-purpose output port setup of DO2 output, and a

setup of high impedance. PN bit performs control setup of an external charge pump for DO1/2 pins as P/N

output.

Unlock F/F detects the phase difference of a programmable counter division output and reference

frequency to the timing from which about 180 degrees of phases shifted. When a phase does not suit at this

time (that is unlock status), unlock F/F is set. The unlock F/F status is reset whenever the UNLOCK

RESET bit is set to “1”.

It is necessary to access to UNLOCK F/F after establishing more time than is required for the reference

frequency cycle after the unlock F/F has been reset in order to detect the phase difference with the

reference frequency cycle. It is for this purpose that the enable bit has been made available, but the unlock

F/F must not be accessed before it has been confirmed that the unlock enable has been set at “1”.

Note: When P/N output and DO output are set up in PLL off-mode state, these outputs are high impedance.

This state is held when PLL off-mode or clock stop mode is set up at outputting “L” or “H” level of DO2

pin.

Note: When PN output is setup, “H” level of DO1/2 pin is output as VDD level and Vreg potential (1.5 V) is

output as “H” level for other settings.

DO2 control

φL19

UNLOCK

RESET

DO2 output setting

Unlock F/F and unlock enable are reset whenever the data is set to “1”.

UNLOCK

φK19

F/F

ENA

Unlock enable

0: PLL unlock detection stand-by

1: PLL unlock detection enabled

0: PLL lock status

1: PLL unlock status

Unlock detection bit

DO2 Output Status DO1 Output Status

DO output

“L” level

“H” level

“HZ”

DO output

N output

P output

PN output setting

TC9328AF Datasheet(PDF) 43 Page - Toshiba Semiconductor

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