TC9328AF datasheet(25/84 Pages) TOSHIBA

25 / 84 page

TC9328AF

2004-09-13

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System Reset

The device’s system will be reset when the RESET pin is subject to the “L” level or when a voltage of 0

V → 0.9 V or more is supplied to the VDD pin (power-on reset). The program will start from 0 address

immediately after about 100 ms stand-by time. The RESET pin should be fixed at the “H” level as the

power-on reset function is used under normal condition.

Note: A power-on reset function can be forbidden with Al switch. Please specify power-on reset prohibition and

use in ES order request sheet. In case of forbidden the power-on reset function, reset with a RESET

pin.

Note: The LCD common signal and the segment output will be fixed at the “L” level during system reset and the

subsequent stand-by period.

Note: Among the internal port shown in the above I/O map, the port which is not initialized after the system

reset should be initialized by the program. The inside port on the I/O map, the port or bit with

mark on

I/O map is set to “0” after system reset and the port or bit with

mark is set to “1”. The port or bit with no

mark is unfixed.

Note: When power supply voltage may become below 0.9 V, set up the clock stop mode or operate the reset

function. The CPU operations are reset when a power supply voltage is re-apply from 0.3 to 0.6 V.

(Power-on reset)

φL2F

OUT2

I/O

φL2D

I/O control -1

-0

-1

-2

-3

φL1

OUT1

I/O

Code

Reference select

Programmable

counter

P16

After system reset, this

port is set to “0”.

After system reset, this

port is set to “1”.

After system reset, this bit

is unfixed.

CPU

operation

VDD pin

RESET

GND

XOUT pin

Internal reset

signal

Reset

Stand-by

(about 100 ms)

CPU operation

Stand-by

(about 100 ms)

CPU

operation

Stand-by

(about 100 ms)

(Note)

GND

A crystal oscillator stops during

the reset from a reset pin.

TC9328AF Datasheet(PDF) 25 Page - Toshiba Semiconductor

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