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TC9328AF Datasheet(PDF) 17 Page - Toshiba Semiconductor

Part # TC9328AF
Description  Portable Audio DTS Controller (DTS-21)
PDF  84 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC9328AF Datasheet(HTML) 17 Page - Toshiba Semiconductor

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TC9328AF
2004-09-13
17
13. Table of Instruction Functions and Operational Instructions
(Description of the symbols used in the table)
M
; Data memory address.
Normally one of the addresses among the addresses 000H to 03FH in the data
memory.
M*
; Data memory address (256 words)
One of the addresses among the addresses 000H to 0FFH in the data memory.
(Effective only when ST and LD instruction are executed.)
r
; General register
One of the addresses among the addresses 000H to 00FH in the data memory.
PC
; Program Counter (14 bits)
STACK
; Stack register (14 bits)
G
; G-register (6 bits)
DATA
; Data register (16 bits)
I
; Immediate data (4 bits)
I*
; Immediate data (6 bits, effective only when STIG instruction is executed.)
N
; Bit position (4 bits)
⎯
; ALL “0”
C
; Port code No. (4 bits)
CN
; Port code No. (4 bits)
RN
; General register No. (4 bits)
ADDR1
; Program memory address (14 bits)
ADDR2
; Program memory address in the pages from 0 to 3 (12 bits)
ADDR3
; The upper 6 bits of the program memory address in the page 0.
DA
; DAL address register
(14bits, effective only when DAL instruction, DAL bit = 1, is executed.)
Ca
; Carry
CY
; Carry flag
P
; Wait condition
b
; Borrow
IN1~IN3
; The ports used during the execution of instructions from IN1 to IN3
OUT1~OUT3 ; The ports used during the execution of instructions from OUT1 to OUT3
( )
; Contents of the register or data memory
[ ] C
; Contents of the port indicated by the code No. C (4 bits)
[ ]
; Contents of the data memory indicated by the contents of the register or data memory
[ ] P
; Contents of the program memory (16 bits)
IC
; Instruction code (6 bits)
*
; Commands equipped with the skip function
DC
; Data memory column address (4 bits)
DR
; Data memory row address (2 bits)
DR*
; Data memory row address
(4 bits, effective only when ST and LD instruction is executed)
(M) b0~(M) b3 ; Bit data of the contents of a data memory (1 bit)



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