TC9328AF datasheet(29/84 Pages) TOSHIBA

29 / 84 page

TC9328AF

2004-09-13

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Interrupt Function

The peripheral hardware which can use Interrupt function has INTR1 pin, INTR2 pin, Timer counter,

and Serial interface.

The peripheral hardware fulfill conditions, Interrupt demand signal from peripheral hardware is all

input, and Interrupt demand is transmitted. When it is received, it branches out vector address determined

by each Interrupt factor. Each Interrupt processing routine is started. The pretreatment for returning to

the same state as the time of Interrupt, before and after usually carrying out Interrupt processing, and

post-processing are required of Interrupt routine. It is necessary to perform shunting and a return for the

a program is returned by the return command for Interrupt.

Interrupt Control Circuit

Interrupt control circuit consists of an Interrupt enable flag, an Interrupt latch, and an Interrupt priority

circuit block. This control performs setup and control by OUT2/IN2 instructions.

(1)

Interrupt enable flag

Interrupt enable flag has an individual permission flag corresponding to a master permission flag

and each Interrupt factor. An individual enable flag sets up prohibition/permission of Interrupt

corresponding to each Interrupt factor. A master enable flag is a flag for which performs

prohibition/permission of all Interrupts. If these enable register is set to “1”, it becomes permission

and is set to “0”, it becomes prohibition. An individual enable flag is accessed with OUT2/IN2

instructions for which [CN = 8H] has been specified to the operand. A master enable flag can perform

permission/prohibition by execution of an EI/DI instruction. A master enable flag is a flag which

performs prohibition/permission of all Interrupts. If these enable register is set to “1”, it becomes

enable and is set to “0”, it becomes prohibition.

In case of forbidding Interrupt in a program, it executes DI instruction, and in case of enabling, it

executes EI instruction. At this time, Interrupt is enabled during the EI instruction execution in a

program, and the DI instruction execution.

If master enable flag is received the Interrupt request, it is reset by “0” and all Interrupts will be in

a prohibition state. By executing of Interrupt return instruction, it is set to “1”. A master enable flag

is read into data memory by IN2 instruction for which [CN = 7H] has been specified.

φLK28

EF1

EF2

EF3

EF4

EF1 • • • INTR1 pin

EF2 • • • INTR2 pin

EF3 • • • Serial interface

EF4 • • • 8-bit timer counter

An individual enable flag

“0” • • • Prohibition

“1” • • • Enable

It’s reset to “0” when it is able to receive interrupt or DI instruction execution.

It’s set to “1” by Interrupt return instruction or EI instruction execution.

φK27

IMF

Master enable flag

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