TC9328AF datasheet(30/84 Pages) TOSHIBA

30 / 84 page

TC9328AF

2004-09-13

(2)

Interrupt latch

If Interrupt request generates, interrupt latch is set to “1”.

If Interrupt is enabled, Interrupt reception will be required of CPU and it will branch Interrupt

routine. If Interrupt is received at this time, Interrupt latch is reset by data “0” automatically.

Interrupt latch data can read by the program and judge individual existence or nothing of interrupt

generating. By interrupt request, interrupt latch is reset from “1” from setting “0”, it is able to cancel

interrupt request or initialization.

(3)

Interrupt priority circuit block

Interrupt priority circuit is a circuit of determined the ranking of the interrupt generating when

interrupt occurs simultaneously or interrupt permit after two or more interrupts had occurred. Vector

address to interrupt routine is also generated by this block.

Priority

Interrupt Factor

Vector Address

INTR1 pin

0001H

INTR2 pin

0002H

Serial interface

0003H

Timer counter

0004H

φL29

ILR1

ILR2

ILR3

ILR4

Interrupt latch reset

If it’s set to “1”, interrupt latch is reset to “0”.

0: No interrupt existence

1: Interrupt existence

φK29

ILR1

ILR2

ILR3

ILR4

ILR1 • • • INTR1 pin

ILR2 • • • INTR2 pin

ILR3 • • • Serial interface

ILR4 • • • 8-bit timer counter

Interrupt latch data

If the interrupt request, it’s set to “1”, receiving

interrupt, It’s reset to “0”.

TC9328AF Datasheet(PDF) 30 Page - Toshiba Semiconductor

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