TC9328AF datasheet(12/84 Pages) TOSHIBA

12 / 84 page

TC9328AF

2004-09-13

Description of Operations

○

CPU

The CPU consists of a program counter, a stack register, ALU, a program memory, a data memory,

G-register, a data register, DAL address register, carry F/F, a judgment circuit, and an interruption circuit.

Program Counter (PC)

The program counter consists of a 14-bit binary up-counter and addresses the program memory (ROM).

The counter is cleared when the system is reset and the programs start from the 0 address.

Under normal conditions, the counter is increased in increments of one whenever an instruction is

executed, but the address specified in the instruction operand is loaded when a JUMP instruction or CALL

instruction is executed.

Also, when an instruction that is equipped with the skip function (AIS, SLTI, TMT, RNS instructions,

etc.) is executed and result of this includes a skip condition, the program counter is increased in increments

of two and the subsequent instruction is skipped. Furthermore, if interruption is received, the vector

address corresponding to each interruption is loaded.

Note: Program memory (ROM) It is 0000H-0FFFH address.

For this reason, an access setup to the address beyond this is forbidden.

Contents of Program Counter (PC)

Instruction

PC13 PC12 PC11 PC10

PC9

PC8

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

JUMP ADDR1

JUMP ADDR2

Power on reset

RESET by reset pin

DAL (DA)

(DAL bit

= 1)

RN, RNS, RNI

At the time of an

interruption reception

Power on reset

RESET by reset pin

Priority

Interruption Factor

Vector Address

INTR1 pin

0001H

INTR2 pin

0002H

Serial inter face

0003H

Timer counter

0004H

Stack Register

A register consisting of 8 × 14 bits which stores the contents of the program counter +1 (the return

address) when a sub-routine call instruction is executed, or an interrupt is processed. The contents of the

stack register are loaded into the program counter when the return instruction (RN, RNS, RNI instruction)

is executed.

There are eight stack levels available and nesting occurs up to eight levels.

Operand of instruction (ADDR1)

DAL address register (DA)

Contents of stack register

Vector address of each interruption

Operand of instruction (ADDR2)

Contents of general

Operand of

instruction (ADDR3)

TC9328AF Datasheet(PDF) 12 Page - Toshiba Semiconductor

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