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TC9328AF Datasheet(PDF) 27 Page - Toshiba Semiconductor |
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TC9328AF Datasheet(HTML) 27 Page - Toshiba Semiconductor |
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27 / 84 page  TC9328AF 2004-09-13 27 (3) Clock stop mode timing ① MODE-0 (The clock stop mode is assumed when the CKSTP is executed during the “L” level of the HOLD input.) ② MODE-1 (The clock stop mode is assumed whenever the CKSTP instruction is executed.) (4) Example of a back-up circuit (example of a MODE-0 circuit) CPU operation High impedance Clock stop CPU operation NOOP operation CKSTP instruction execution NOOP operation XOUT pin CKSTP instruction Stand-by (about 100 ms) HOLD pin CPU operation High impedance Clock stop CKSTP instruction execution HOLD pin XOUT pin CKSTP instruction CKSTP instruction execution Stand-by (about 100 ms) CPU operation Clock stop Example of a battery back-up circuit Example of a capacitor back-up circuit 42 31 50 1 M Ω HOLD VDD VDD POWER 42 31 50 1 M Ω HOLD VDD VDD POWER |
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