TC9328AF datasheet(28/84 Pages) TOSHIBA

28 / 84 page

TC9328AF

2004-09-13

Wait Mode

The wait mode suspends system operations, maintains the internal status immediately prior to

suspension and reduces current consumption. There are two types of wait mode available; the SOFT WAIT

mode and the HARD WAIT mode. It is suspended at the address of the WAIT instruction execution when

the WAIT mode is activated. The next address is executed immediately after the wait mode is cancelled

without entering a stand-by status.

(1)

SOFT WAIT mode

Only the CPU operations within the device are suspended when the WAIT instruction in which [P =

0H] has been specified in the operand is executed. The crystal resonator and other elements will

continue to operate normally at this time. The SOFT WAIT mode is efficient in reducing current

consumption during clock operations used in programs that include clock functions.

Note: Current consumption will differ in accordance with execution time of CPU operation.

(2)

HARD WAIT mode

The operations of all elements, with the exception of the crystal resonator, can be suspended by the

execution of the WAIT instruction in which [P = 1H] has been specified in the operand. This enables

even greater levels of current consumption reduction than the SOFT WAIT mode. It suspends the

CPU operation.

Note: The output port is maintained during the HARD WAIT mode. All LCD display output pin are fixed “L”

level and voltage doubler circuit (VDB), constant voltage circuit for LCD (VEE) and voltage doubler

circuit for LCD (VLCD) are operated.

(3)

Wait mode setting

The wait status is assumed whenever the WAIT instruction is executed.

Note: The PLL OFF status will be assumed during the wait mode.

(4)

Wait mode cancellation conditions

The wait mode is cancelled when the following conditions are fulfilled:

① When the input status of the HOLD pin changes.

② When the input status of the I/O port specified in the input port (P1-0~3) changes.

③ When the 2 Hz Timer F/F is set to “1” (only with the SOFT WAIT mode)

HOLD Input Port

The HOLD pin can be used as an input port. This bit loads data input with IN1 instruction for which

[CN = 7H] has been specified in the operand into the data memory. It is necessary to access this port prior

to the execution of the Back-up instruction when the clock stop mode or WAIT mode has been set. It is

necessary to note that there are cases when the clock stop mode will not be activated if the Back-up

instruction is executed without this port being accessed.

While HOLD PLL off control bit is set to “1”, if HOLD pin input “L” level, it will become PLL off-mode.

For this reason, a setup in PLL off-mode can be made quickly at the time of battery exchange.

The bit is accessed with the OUT3 instruction for which [CN = 9H] has been specified in the operand. All of

the reference port is “1”, it also becomes PLL off mode. (→ Refer to the reference frequency divider item)

0: Input “L” level

1: Input “H” level

φK17

HOLD

0: Do not control PLL OFF with a HOLD pin

1: PLL OFF mode with “L” level of HOLD pin

φL39

HOLD

PLL

OFF

control

TC9328AF Datasheet(PDF) 28 Page - Toshiba Semiconductor

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