TC9328AF datasheet(64/84 Pages) TOSHIBA

64 / 84 page

TC9328AF

2004-09-13

The pulse counter measures pulse number of INTR2 pin.

POL bit set up the clock edge of input pin. If “0” is set, it will count in the falling of an input and it will

set to “1”, it will count in the rising of an input. Usually, this bit is used fixed.

DOWN bit sets up a up/down of 8-bit counter. If it sets to “0” and it will set to rise count operation and

“1”, down count operation will be done. A change of a up/down can be performed freely. However, if a clock

pulse is inputted during change command execution, since it is canceled, be careful of this count.

When 28 or more pulses are inputted, OVER F/F bit is set to “1”. When performing count operation of

8-bits or more, this OVER F/F are detected, and on a data memory, only the number of times of overflow is

added and subtracted, and can correspond. After detection by this bit, and OVER RESET bit is set “1” and

OVER F/F is reset.CTR RESET bit resets only 8-bit counter. The counter is reset whenever it sets “1”.

Counter data loaded data in a data memory by the binary.

The control of pulse counter and data loading is accessed with the OUT3/IN3 instructions for which [CN

= BH] have been specified in the operand and arranges in DAL address register port. This port is set up by

data select port (φL2D), which specified the division. The data of a specification port is set beforehand and

the data port corresponding to it can be accessed. The data select port is +1 increments whenever it

accesses DAL address port (φL3B, φK3B). For this reason, after setting up a data selection port, it can set

up continuously.

Note: If POL bit is changed, a clock pulse may enter. Reset data by the reset bit after changing.

Note: If data select port is

+1 increments when it accesses φL2E, φL2F, φL3B, φK3B on the I/O map.

Pulse Counter Circuit Configuration

Note: Pulse input is the Schmitt input type.

Note: It can be used as pulse counter and interrupt function (INTR2 pin input) together.

Example for Pulse Counter Timing

PCTRin (INTR2)

OVER RESET

DOWN

PC0~PC7

POL

CTR RESET

To interrupt circuit

8-bit up/down counter

F/F

OVER F/F

Data set to pulse counter

control bit

CTR/OVER RESET

execution

DOWN bit

set to “1”

OVER

RESET execution

DOWN bit

PCTRin input

Counter data

OVER F/F

Pulse width 1

µs (min)

02H

03H

01H

FFH

00H

01H

02H

− 1 N − 2

+ 1

TC9328AF Datasheet(PDF) 64 Page - Toshiba Semiconductor

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