F24 datasheet(5/210 Pages) RENESAS

5 / 210 page

RL78/F23, F24

1. OVERVIEW

R01DS0446EJ0120 Rev.1.20

Page 5 of 207

Dec 31, 2025

1.3.2 RL78/F23 Functions List

Table 1-5. RL78/F23 Functions List (1/2)

Function Items

Series Name

R7F123FMG

R7F123FLG

R7F123FGG

R7F123FBG

Pin Count

80 pins

64 pins

48 pins

32 pins

Code flash

128 KB

Data flash

8 KB

RAM

12 KB

Supply voltage range

2.7 V to 5.5 V

Maximum operation frequency

40 MHz

System clock

Main system

clock oscillator

Crystal / ceramic /

square wave

2 to 20 MHz (operating at 2.7 V to 5.5 V)

High-speed on-chip

oscillator

Normal high accuracy

40 MHz (typ.)

Low-speed on-chip

oscillator

For low-speed operation

15 kHz (typ.)

Subsystem clock oscillator

32.768 kHz Note 6

None

PLL

Yes

Clock for

peripherals

Low-speed on-chip

oscillator

For peripherals other than

WDT

15 kHz (typ.)

For WDT

15 kHz (typ.)

POR

When power supply is rising

1.56 V (typ.)

When power supply is falling

1.55 V (typ.)

LVD

VDD voltage

detection

When power supply is rising

2.81 V (typ.) to 4.74 V (typ.) (in 6 steps)

When power supply is falling

2.75 V (typ.) to 4.64 V (typ.) (in 6 steps)

Functional safety

Note 7

WWDT (window watchdog timer)

Yes

Flash memory fast CRC operation function

Yes

General purpose CRC operation

Yes

Flash memory ECC function

Yes

RAM 1-bit error correction function

Yes

RAM 2-bit error detection function

Yes

Invalid memory access detection function

Yes

Frequency detection function

Yes

Clock monitor function

Yes

Stack pointer monitor function

Yes

A/D test function

Yes

I/O ports

Input/Output

CMOS

68 ch

52 ch

38 ch

25 ch

Output

CMOS

1 ch

None

Input

Shared with oscillator pins

4ch Note 6

2 ch

Input only

1 ch

Power supply pins

For internal circuits

VDD, VSS, REGC

For I/O ports

EVDD0, EVSS0

None

For analog circuits (AD)

VDD, VSS (AVREFP, AVREFM for AD)

Multiply/divide and

multiply-

accumulate

functions

Multiply

16 bits

× 16 bits (signed)

16 bits

× 16 bits (unsigned)

Divide

32 bits

÷ 32 bits (unsigned)

Multiply-accumulate

16 bits

× 16 bits + 32 bits (signed)

16 bits

× 16 bits + 32 bits (unsigned)

Arithmetic instructions (extended instruction set)

Yes

Vectored interrupt

sources

External

15 ch Note 4, 5

14 ch Note3, 5

12 ch Note 2

8 ch Note 1

Internal

38 ch Note 4

38 ch Note 3

38 ch Note 2

38 ch Note 1

Key return detection

8 ch

6 ch

DTC

36 sources

35 sources

Timer

TAU

16 bits (8 ch + 4 ch)

RTC

1 ch

Timer RJ

16 bits

× 1

Timer RDe

16 bits

× 2 (with PWMOPA and dithering / gate function)

(Notes are listed on the next page.)

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