F24 datasheet(61/210 Pages) RENESAS

61 / 210 page

RL78/F23, F24

3. ELECTRICAL SPECIFICATIONS (GRADE 3)

R01DS0446EJ0120 Rev.1.20

Page 61 of 207

Dec 31, 2025

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

(2/2)

Notes 1. Pins RESET, INTP0 to INTP3, INTP12, and INTP13 have noise filters for transient levels lasting less than

100 ns.

2. TA = +25

°C, EVDD0 = 5.0 V

AC Timing Test Points

Test points

VIH

VIL

VIH

VIL

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Interrupt input high-level

width, low-level width

tINTH, tINTL INTP0 to INTP13 Note 1

µs

KR0 to KR7 key interrupt

input low-level width

tKR

250

RESET low-level width

tRSL

Note 1

µs

Port output rise time, port

output fall time

tRO, tFO

P00 to P03, P10 to P17,

P30 to P32, P40 to P47,

P50 to P57, P60 to P67,

P70 to P77, P106, P107,

P120, P125 to P127,

P130, P140, P150 to P157

(normal slew rate)

C = 30 pF

4.0 V

≤ EVDD0 ≤ 5.5 V

2.7 V

≤ EVDD0 < 4.0 V

P10, P12, P14, P30, P120,

P140

(special slew rate)

C = 30 pF

4.0 V

≤ EVDD0 ≤ 5.5 V

25 Note 2

2.7 V

≤ EVDD0 < 4.0 V

100

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