F24 datasheet(85/210 Pages) RENESAS

85 / 210 page

RL78/F23, F24

3. ELECTRICAL SPECIFICATIONS (GRADE 3)

R01DS0446EJ0120 Rev.1.20

Page 85 of 207

Dec 31, 2025

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Reference voltage (+)

AVREFP

2.7

VDD

Analog input voltage

VAIN

ANI0 to ANI5, ANI8 to ANI30

AVREFP

Internal reference voltage (+)

VBGR

2.7 V

≤ VDD ≤ 5.5 V

1.38

1.45

1.5

Analog input slew rate

0.4

V/µs

Operation clock

fAD

MHz

Conversion time Note 4

(per 1 channel)

tCONV

ADCLK = 40 MHz, input impedance ≤ 0.5 kΩ

ANI0 to ANI5, ANI8 to ANI15 Note 2

1.125

µs

ANI16 to ANI30

1.8

µs

ANI1, ANI2 Note 3

2.1

µs

Notes 1. Excludes quantization error (

±1/2 LSB).

2. In case that dedicated sample & hold circuit is not used.

3. In case that dedicated sample & hold circuit is used.

4. The A/D conversion processing time (tCONV) consists of sampling time and time for conversion by successive

approximation.

(2/2)

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