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F24 Datasheet(PDF) 82 Page - Renesas Technology Corp |
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F24 Datasheet(HTML) 82 Page - Renesas Technology Corp |
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82 / 210 page ![]() RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 82 of 207 Dec 31, 2025 3.5.2 Serial Interface IICA (TA = -40 to +105 °C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions Normal Mode Fast Mode Fast Mode Plus Unit MIN. MAX. MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode plus: 10 MHz ≤ fMCK 0 1000 kHz Fast mode: 3.5 MHz ≤ fMCK 0 400 kHz Normal mode: 1 MHz ≤ fMCK 0 100 kHz Setup time of restart condition Note 1 tSU:STA 4.7 0.6 0.26 µs Hold time tHD:STA 4.0 0.6 0.26 µs Hold time when SCLA0 = “L” tLOW 4.7 1.3 0.5 µs Hold time when SCLA0 = “H” tHIGH 4.0 0.6 0.26 µs Data setup time (reception) tSU:DAT 250 100 50 ns Data hold time (transmission) Note 2 tHD:DAT 0 3.45 0 0.9 0 µs Setup time of stop condition tSU:STO 4.0 0.6 0.26 µs Bus-free time tBUF 4.7 1.3 0.5 µs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ Fast mode: Cb = 320 pF, Rb = 1.1 kΩ Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing tLOW SCLA0 SDAA0 Stop condition tR tHD:DAT tHD:STA tHIGH tF tSU:DAT tSU:STA tHD:STA tSU:STO Start condition Restart condition Stop condition tBUF <R> <R> <R> |
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