F24 datasheet(89/210 Pages) RENESAS

89 / 210 page

RL78/F23, F24

3. ELECTRICAL SPECIFICATIONS (GRADE 3)

R01DS0446EJ0120 Rev.1.20

Page 89 of 207

Dec 31, 2025

3.7 Power Supply Voltage Rising Time

(TA = -40 to +105

°C, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Maximum power supply voltage

rising slope

Svrmax

0 V

→ VDD (VPOC2 = 0 or 1 Note 2)

50 Note 3

V/ms

Minimum power supply voltage

rising slope Note 1

Svrmin

0 V

→ 2.7 V

6.5

V/ms

Notes 1. The minimum power supply voltage rising slope is applied only under the following condition.

When the voltage detection (LVD) circuit is not used (VPOC2 = 1) and an external reset circuit is not used or

when a reset is not effected until VDD = 2.7 V.

2. These values indicate setting values of option bytes.

3. If the power supply drops below VPDR and a POR reset is effected, this specification is also applied when the

power supply is recovered without dropping to 0 V.

3.8 Regulator Output Voltage Characteristics

(TA = -40 to +105

°C, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

REGC output voltage Note

VOREGC

C = 0.47 to 1 µF

2.0

2.1

2.2

Note Other than the following conditions are applicable.



In STOP mode.



When the high-speed system clock (fMX), the high-speed on-chip oscillator clock (fIH), and PLL clock (fPLL) are

stopped during CPU operation with the subsystem/low-speed on-chip oscillator clock select clock (fSL).



When the hifh-speed system clock (fMX), the high-speed on-chip oscillator clock (fIH), and PLL clock (fPLL) are

stopped during the HALT mode when the CPU operation with the subsystem/low-speed on-chip oscillator

clock select (fSL) has been set.

3.9 RAM Data Retention Characteristics

(TA = -40 to +105

°C, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data retention supply voltage

VDDDR

1.47 Note

5.5

Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage

reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.

Standby release signal

(interrupt request)

RAM data retention

STOP instruction execution

STOP mode

Operation mode

VDDDR

VDD

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