F24 datasheet(87/210 Pages) RENESAS

87 / 210 page

RL78/F23, F24

3. ELECTRICAL SPECIFICATIONS (GRADE 3)

R01DS0446EJ0120 Rev.1.20

Page 87 of 207

Dec 31, 2025

3.6.2 D/A Converter Characteristics

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

RES

bit

Overall error

AINL

Rload = 4 M

2.7 V

≤ VDD ≤ 5.5 V

±2.5

LSB

Rload = 8 M

2.7 V

≤ VDD ≤ 5.5 V

±2.5

LSB

Settling time

tSET

Cload = 20 pF

2.7 V

≤ VDD ≤ 5.5 V

µs

3.6.3 Comparator Characteristics

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input offset voltage

VIOCMP

±5

±40

Input voltage range

VICMP

VDD

Response time

tCR, tCF

Input amplitude

±100 mV

200

Stabilization wait time during input

channel switching Note 1

tWAIT

Input amplitude

±100 mV

300

Operation stabilization wait time Note 2

tCMP

3.3 V

≤ VDD ≤ 5.5 V

µs

2.7 V

≤ VDD < 3.3 V

µs

Notes 1. Period of time from when the comparator input channel is switched until the comparator is switched to output.

2. Period of time from when the comparator operation is enabled (HCMPON bit in CMPCTL is set to 1) until the

comparator satisfies the DC/AC characteristics.

3.6.4 POR Circuit Characteristics

(TA = -40 to +105

°C, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Detection voltage Note 1

VPOR

Power supply rise time

1.48

1.56

1.62

VPDR

Power supply fall time

1.47

1.55

1.61

Minimum pulse width Note 2

TPW

300

µs

Detection delay time

TPD

350

µs

Notes 1. This indicates the POR circuit characteristics, and normal operation is not guaranteed under the condition of

less than lower limit operation voltage (2.7 V).

2. Minimum time required for a POR reset when VDD exceeds below VPDR.

Supply voltage (VDD)

TPW

VPOR

VPDR

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