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F24 Datasheet(PDF) 113 Page - Renesas Technology Corp

Part # F24
Description  RENESAS MCU
PDF  210 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

F24 Datasheet(HTML) 113 Page - Renesas Technology Corp

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RL78/F23, F24
4. ELECTRICAL SPECIFICATIONS (GRADE 4)
R01DS0446EJ0120 Rev.1.20
Page 113 of 207
Dec 31, 2025
4.4 AC Characteristics
4.4.1 Basic Operation
(TA = -40 to +125
°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Instruction cycle (minimum
instruction execution time)
TCY
High-speed on-chip oscillator clock operation
0.025
0.5
µs
High-speed system clock operation
0.05
0.5
µs
PLL clock operation
0.025
0.5
µs
Subsystem clock operation
28.5
30.5
34.5
µs
Low-speed on-chip oscillator clock operation
66.6
µs
In self programming mode
0.025
0.5
µs
CPU/peripheral hardware
clock frequency
fCLK
0.025
66.6
µs
External system clock
frequency
fEX
2.0
20.0
MHz
fEXS
29
35
kHz
External system clock input
high-level width, low-level
width
tEXH, tEXL
24
ns
tEXHS, tEXLS
13.7
µs
TI00 to TI07, TI10 to TI17
input high-level width, low-
level width
tTIH, tTIL
1/fMCK+10
ns
TO00 to TO07,
TO10 to TO17,
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRJIO0, TRJO0
output frequency
fTO
Normal slew rate,
C = 30 pF
4.0 V
≤ EVDD0 ≤ 5.5 V
16
MHz
2.7 V
≤ EVDD0 < 4.0 V
8
MHz
TO01, TO06, TO07,
TO11, TO13,
TRDIOC0, TRDIOD0,
TRDIOD1, TRJO0 only,
Special slew rate,
C = 30 pF
2
MHz
PCLBUZ0 output frequency
fPCL
Normal slew rate
C = 30 pF
4.0 V
≤ EVDD0 ≤ 5.5 V
16
MHz
2.7 V
≤ EVDD0 < 4.0 V
8
MHz
Special slew rate
C = 30 pF
2
MHz
Timer RJ input cycle
tC
TRJIO0
100
ns
Timer RJ input high-level
width, low-level width
tTJIH, tTJIL
TRJIO0
40
ns
Timer RDe input high-level,
low-level width
tTDIH, tTDIL
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1,
TRDCLK0, TRD0RES, TRD1RES
3/fTRD
ns
Timer RDe pulse output
forced cutoff signal low-level
width
tTDSIL
P137/INTP0
2MHz < fCLK
≤ 40MHz
1
µs
fCLK
≤ 2 MHz
1/fCLK + 1
µs
Caution Excluding the error in oscillation frequency accuracy.
Remarks 1. fMCK: Timer array unit operation clock frequency
2. fTRD: Timer RDe operation clock frequency



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