F24 datasheet(120/210 Pages) RENESAS

120 / 210 page

RL78/F23, F24

4. ELECTRICAL SPECIFICATIONS (GRADE 4)

R01DS0446EJ0120 Rev.1.20

Page 120 of 207

Dec 31, 2025

(4)

During communication at same potential (CSI mode) (slave mode, SCKp … external clock input, normal slew

rate)

(TA = -40 to +125

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY2

32 MHz

< fMCK

10/fMCK

fMCK

≤ 32 MHz

8/fMCK

SCKp high-level width,

low-level width

tKH2, tKL2

tKCY2/2

SIp setup time

(to SCKp

↑) Note 1

tSIK2

1/fMCK + 20

SIp hold time

(from SCKp

↑) Note 2

tKSI2

1/fMCK + 31

Delay time from SCKp

↓ to

SOp output Note 3

tKSO2

C = 30 pF

Note 4

4.0 V

≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V

2/fMCK + 44

2.7 V

≤ VDD = EVDD0 = EVDD1 < 4.0 V

2/fMCK + 57

SSIp setup time

tSSIK

DAP = 0

120

DAP = 1

1/fMCK + 120

SSIp hold time

tKSSI

DAP = 0

1/fMCK + 120

DAP = 1

120

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The Slp setup time becomes “to SCKp

↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1.

The SIp hold time becomes “from SCKp

↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The delay time to SOp output becomes “from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and

CKPmn = 0.

4. C is the load capacitance of the SCKp and SOp output lines.

Caution Select the normal input buffer for the SIp, SCKp and SSIp pins and normal output mode for the SOp

pin.

Remarks 1. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1)

2. fMCK: Serial array unit operation clock frequency

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