F24 datasheet(170/210 Pages) RENESAS

170 / 210 page

RL78/F23, F24

5. ELECTRICAL SPECIFICATIONS (GRADE 5)

R01DS0446EJ0120 Rev.1.20

Page 170 of 207

Dec 31, 2025

(2)

During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, normal

slew rate)

(TA = -40 to +150

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY1

150 Note 5

SCKp high-level width, low-level width

tKH1, tKL1

4.0 V

≤ EVDD0 ≤ 5.5 V

tKCY1/2 – 12

2.7 V

≤ EVDD0 < 4.0 V

tKCY1/2 – 18

SIp setup time (to SCKp

↑) Note 1

tSIK1

4.0 V

≤ EVDD0 ≤ 5.5 V

2.7 V

≤ EVDD0 < 4.0 V

SIp hold time (from SCKp

↑) Note 2

tKSI1

Delay time from SCKp

↓ to SOp output Note 3

tKSO1

C = 30 pF Note 4

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The Slp setup time becomes “to SCKp

↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1.

The SIp hold time becomes “from SCKp

↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The delay time to SOp output becomes “from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and

CKPmn = 0.

4. C is the load capacitance of the SCKp and SOp output lines.

5. tKCY1 ≥ 4/fMCK must also be satisfied.

Caution Select the normal input buffer for the SIp pin and normal output mode for the SOp pin and SCKp pin.

Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1)

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