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F24 Datasheet(PDF) 208 Page - Renesas Technology Corp |
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F24 Datasheet(HTML) 208 Page - Renesas Technology Corp |
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208 / 210 page  R01DS0446EJ0120 Rev.1.20 (A−1) Dec 31, 2025 REVISION HISTORY RL78/F23, F24 Datasheet Rev Date Description Page Summary 1.10 Jun 30, 2024 ‒ First edition issued. 1.20 Dec 31, 2025 2 Modification of Table 1-1. RL78/F23, F24 Lineup (Grade-3) 2 Modification of Table 1-2. RL78/F23, F24 Lineup (Grade-4) 2 Modification of Table 1-3. RL78/F23, F24 Lineup (Grade-5) 16 Modification of Figure 1-10. RL78/F24 Pin Configuration for 100-pin Products 17 Modification of Figure 1-11. RL78/F24 Pin Configuration for 80-pin Products 18 Modification of Figure 1-12. RL78/F23 Pin Configuration for 80-pin Products 19 Modification of Figure 1-13. RL78/F24 Pin Configuration for 64-pin Products 20 Modification of Figure 1-14. RL78/F23 Pin Configuration for 64-pin Products 21 Modification of Figure 1-15. RL78/F24 Pin Configuration for 48-pin Products 22 Modification of Figure 1-16. RL78/F23 Pin Configuration for 48-pin Products 23 Modification of Figure 1-17. RL78/F24 Pin Configuration for 32-pin Products 24 Modification of Figure 1-18. RL78/F23 Pin Configuration for 32-pin Products 65 Modification of Note 5 in (2) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 66 Modification of Note 5 in (3) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, special slew rate) 76 Modification of Note 3 in (9) During communication at different potential (3-V supply system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 82 Modification of 3.5.2 Serial Interface IICA 118 Modification of Note 5 in (2) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 119 Modification of Note 5 in (3) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, special slew rate) 129 Modification of Note 3 in (9) During communication at different potential (3-V supply system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 135 Modification of 4.5.2 Serial Interface IICA 170 Modification of Note 5 in (2) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 171 Modification of Note 5 in (3) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, special slew rate) 181 Modification of Note 3 in (9) During communication at different potential (3-V supply system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 187 Modification of 5.5.2 Serial Interface IICA 198 Modification of 6.1 32-pin Products 199 Addition of Figure PWQN0032KH-A in 6.1 32-pin Products All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. |
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