WM8959 datasheet(129/155 Pages) WOLFSON

129 / 155 page

Pre-Production

WM8959

PP, May 2008, Rev 3.1

129

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:2

00b

Reserved - Do Not Change

DACL_ENA

(rw)

Left DAC Enable

0 = disabled

1 = enabled

DACR_ENA

(rw)

Right DAC Enable

0 = disabled

1 = enabled

15:9

0100000b

Reserved - Do Not Change

AIF_BCLK_INV

BCLK Invert

0 = BCLK not inverted

1 = BCLK inverted

Right, left and I2S modes – DACLRC polarity

0 = normal DACLRC polarity

1 = invert DACLRC polarity

AIF_LRCLK_INV

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising edge after DACLRC

rising edge (mode A)

1 = MSB is available on 1st BCLK rising edge after DACLRC

rising edge (mode B)

6:5

AIF_WL

[1:0]

10b

Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

4:3

AIF_FMT

[1:0]

10b

Digital Audio Interface Format

00 = Right justified

01 = Left justified

10 = I2S Format

11 = DSP Mode

R04 (04h)

Audio

Interface (1)

2:0

000b

Reserved - Do Not Change

DACL_SRC

Left DAC Data Source Select

0 = Left DAC outputs left channel data

1 = Left DAC outputs right channel data

DACR_SRC

Right DAC Data Source Select

0 = Right DAC outputs left channel data

1 = Right DAC outputs right channel data

AIFDAC_TDM

DAC TDM Enable

0 = Normal DACDAT operation

1 = TDM enabled on DACDAT

AIFDAC_TDM_

CHAN

DACDAT TDM Channel Select

0 = DACDAT data input on slot 0

1 = DACDAT data input on slot 1

11:10

DAC_BOOST

[1:0]

00b

DAC Input Volume Boost

00 = 0dB

01 = +6dB (Input data must not exceed -6dBFS)

10 = +12dB (Input data must not exceed -12dBFS)

11 = +18dB (Input data must not exceed -18dBFS)

9:5

00000b

Reserved - Do Not Change

DAC_COMP

DAC Companding Enable

0 = disabled

1 = enabled

R05 (05h)

Audio

Interface (2)

DAC_COMPMODE

DAC Companding Type

0 = µ-law

1 = A-law

WM8959 Datasheet(PDF) 129 Page - Wolfson Microelectronics plc

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