WM8959 datasheet(130/155 Pages) WOLFSON

130 / 155 page

WM8959

Pre-Production

PP, May 2008, Rev 3.1

130

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

000b

Reserved - Do Not Change

TOCLK_RATE

Timeout Clock Rate

(Selects clock to be used for volume update timeout and

GPIO input de-bounce)

0 = SYSCLK / 221 (Slower Response)

1 = SYSCLK / 219 (Faster Response)

TOCLK_ENA

Timeout Clock Enable

(This clock is required for volume update timeout and GPIO

input de-bounce)

0 = disabled

1 = enabled

Reserved - Do Not Change

12:9

OPCLKDIV

[3:0]

0000b

GPIO Output Clock Divider

0000 = SYSCLK

0001 = SYSCLK / 2

0010 = SYSCLK / 3

0011 = SYSCLK / 4

0100 = SYSCLK / 5.5

0101 = SYSCLK / 6

0110 = SYSCLK / 8

0111 = SYSCLK / 12

1000 = SYSCLK / 16

1001 to 1111 = Reserved

8:6

DCLKDIV

[2:0]

111b

Class D Clock Divider

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

Reserved - Do Not Change

4:1

BCLK_DIV

[3:0]

0100b

BCLK Frequency (Master Mode)

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4

0101 = SYSCLK / 5.5

0110 = SYSCLK / 6

0111 = SYSCLK / 8

1000 = SYSCLK / 11

1001 = SYSCLK / 12

1010 = SYSCLK / 16

1011 = SYSCLK / 22

1100 = SYSCLK / 24

1101 = SYSCLK / 32

1110 = SYSCLK / 44

1111 = SYSCLK / 48

R06 (06h)

Clocking (1)

Reserved - Do Not Change

R07 (07h)

Reserved - Do Not Change

WM8959 Datasheet(PDF) 130 Page - Wolfson Microelectronics plc

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