WM8959 datasheet(131/155 Pages) WOLFSON

131 / 155 page

Pre-Production

WM8959

PP, May 2008, Rev 3.1

131

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK

1 = PLL output

CLK_FORCE

Forces Clock Source Selection

0 = Existing SYSCLK source (MCLK or PLL output) must be

active when changing to a new clock source.

1 = Allows existing MCLK source to be disabled before

changing to a new clock source.

12:11

MCLK_DIV

[1:0]

00b

SYSCLK Pre-divider. Clock source (MCLK or PLL output) will

be divided by this value to generate SYSCLK.

00 = Divide SYSCLK by 1

01 = Reserved

10 = Divide SYSCLK by 2

11 = Reserved

MCLK_INV

MCLK Invert

0 = Master clock not inverted

1 = Master clock inverted

9:5

00000b

Reserved - Do Not Change

4:2

DAC_CLKDIV

[2:0]

000b

DAC Sample Rate Divider

000 = SYSCLK / 1.0

001 = SYSCLK / 1.5

010 = SYSCLK / 2.0

011 = SYSCLK / 3.0

100 = SYSCLK / 4.0

101 = SYSCLK / 5.5

110 = SYSCLK / 6.0

111= Reserved

Clocking (2)

1:0

00b

Reserved - Do Not Change

AIF_MSTR1

Audio Interface 1 Master Mode Select

0 = Slave mode

1 = Master mode

AIF_MSTR2

Audio Interface 2 Master Mode Select

0 = Slave mode

1 = Master mode

AIF_SEL

Audio Interface Select

0 = Audio interface 1

1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2,

GPIO5/DACDAT2)

R08 (08h)

Audio

Interface (3)

12:0

0040h

Reserved - Do Not Change

GPIO1_ENA

GPIO1 Enable

0 = GPIO1 not enabled

1 = GPIO1 enabled

Reserved - Do Not Change

AIF_TRIS

Audio Interface and GPIO Tristate

0 = Audio interface and GPIO pins operate normally

1 = Tristate all audio interface and GPIO pins

Reserved - Do Not Change

R09 (09h)

Audio

Interface (4)

DACLRC_DIR

DACLRC Direction

(Forces DACLRC clock to be output in slave mode)

0 = DACLRC normal operation

1 = DACLRC clock output enabled

WM8959 Datasheet(PDF) 131 Page - Wolfson Microelectronics plc

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