C511 datasheet(67/128 Pages) SIEMENS

67 / 128 page

Semiconductor Group

6-34

On-Chip Peripheral Units

6.3.4 Details about Mode 0

Serial data enters and exists through RXD. TXD outputs the shift clock. 8 data bits are transmitted/

received: (LSB first). The baud rate is fixed at

OSC/12.

Figure 6-15a shows a simplyfied functional diagram of the serial port in mode 0. The associated

timing is illustrated in figure 6-b.

Transmission is initiated by any instruction that uses SBUF as a destination register. The "WRITE

to SBUF" signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells

the TX control block to commence a transmission. The internal timing is such that one full machine

cycle will elapse between "WRITE to SBUF", and activation of SEND.

SEND enables the output of the shift register to the alternate output function line of P3.0, and also

enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during

S3, S4, and S5 of every machine cycle, and high during S6, S1 and S2. At S6P2 of every machine

cycle in which SEND is active, the contents of the transmit shift register are shifted to the right one

position.

As data bits shift out to the right, zeroes come in from the left. When the MSB of the data byte is at

the output position of the shift register, then the 1 that was initialy loaded into the 9th position, is just

to the left of the MSB, and all positions to the left of that contain zeroes. This condition flags the TX

control block to do one last shift and then deactivate SEND and set TI. Both of these actions occur

at S1P1 of the 10th machine cycle after "WRITE to SBUF".

Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the

RX control unit writes the bits 1111 1110 to the receive shift register, and in the next clock phase

activates RECEIVE.

RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK

makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in

which RECEIVE is active, the contents of the receive shift register are shifted to the left one position.

The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the

same machine cycle.

As data bit comes in from the right, 1s shift out to the left. When the 0 that was initially loaded into

the rightmost position arrives at the leftmost position in the shift register, it flags the RX control block

to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that

cleared RI, RECEIVE is cleared and RI is set.

C511 Datasheet(PDF) 67 Page - Siemens Semiconductor Group