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C511 Datasheet(PDF) 84 Page - Siemens Semiconductor Group |
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C511 Datasheet(HTML) 84 Page - Siemens Semiconductor Group |
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84 / 128 page  On-Chip Peripheral Units Semiconductor Group 6-51 6.4.8.2 SSC Interrupt Enable Register SCIEN This byte addressable register enables or diasables interrupt request for the status bits. This register must only be written when the SSC interrupts are disabled in the general interrupt enable register IE (A8H), otherwise unexpected interrupt requests may occur. Special Function Registers SCIEN (Address F9H) Reset Value : XXXXXX00B Note: The SSC interupt behaviour is in addition affected by bit ESSC in the interrupt enable register IE and by bit PSSC of the interrupt priority register IP. Bit Function – Not implemented. Reserved for future use. During reads these bits will be undefined. WCEN Write Collision Interrupt Enable WCEN =0 : No interrupt request will be generated if the WCOL bit in the status register SCF is set. WCEN=1 : An interrupt is generated if the WCOL bit in the status register SCF is set. TCEN Transfer Completed Interrupt Enable TCEN =0 : No interrupt request will be generated if the TC bit in the status register SCF is set. TCEN=1 : An interrupt is generated if the TC bit in the status register SCF is set. – ––– F9H SCIEN Bit No. 7 65 43 21 0 MSB LSB –– WCEN TCEN |
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