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C511 Datasheet(PDF) 94 Page - Siemens Semiconductor Group |
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C511 Datasheet(HTML) 94 Page - Siemens Semiconductor Group |
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94 / 128 page ![]() Interrupt System Semiconductor Group 7-7 7.3 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1) An interrupt of equal or higher priority is already in progress. 2) The current (polling) cycle is not in the final cycle of the instruction in progress. 3) The instruction in progress is RETI or any write access to registers IE or IP. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IE or IP, then at least one more instruction will be executed before any interrupt is vectored too; this delay guarantees that changes of the interrupt status can be observed by the CPU. The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the pending interrupt requests. The polling cycle/LCALL sequence is illustrated in figure 7-2. Figure 7-2 Interrupt Response Timing Diagram MCT01859 S5P2 Interrupt is latched Interrupts are polled Vector Address Long Call to Interrupt Routine Interrupt C2 C1 C3 C4 C5 |
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