C511 datasheet(24/128 Pages) SIEMENS

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Memory Organization

Semiconductor Group

3-4

If the XRAM is enabled these instruction will only access the internal XRAM. External memory

cannot be accessed in this case because no external bus cycle will be generated. Therefore, port

0 and 3 can be used as standard I/O, if only the internal XRAM is used.

3.4

General Purpose Registers

The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose

registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program

status word PSW, RS1 and RS0, select the active register bank (see description of the PSW in

chapter 2.1). This allows fast context switching, which is useful when entering subroutines or

interrupt service routines. After reset register bank 0 is selected.

The 8 general purpose registers of the selected register bank may be accessed by register

addressing. With register addressing the instruction opcode indicates which register is to be used.

For indirect addressing R0 and R1 are used as pointer or index register to address internal or

external memory (e.g. MOV @R0).

Reset initializes the stack pointer to location 07H and increments it once to start from location 08H

which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one

data storage.

3.5

Special Function Registers

All registers except the program counter and the four general purpose register banks reside in the

special function register area.

The 34 special function registers (SFR) include pointers and registers that provide an interface

between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits

within the SFR area.

All SFRs are listed in table 3-1 and table 3-2. In table 3-1 they are organized in groups which refer

to the functional blocks of the C511/513. Table 3-2 illustrates the contents of the SFRs, e.g. the bits

of the SFRs.

Table 3-2

Contents of the SFRs, SFRs in Numeric Order of their Addresses

Addr

Content

after

Reset 1)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

80H

FFH

81H

07H

82H

DPL

00H

83H

DPH

00H

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