C511 datasheet(93/128 Pages) SIEMENS

93 / 128 page

Semiconductor Group

7-6

Interrupt System

If two interrupt requests of different priority level are received simultaneously, the request of higher

priority is serviced. If requests of the same priority are received simultaneously, an internal polling

sequence determines which request is serviced. Thus within each priority level there is a second

priority structure determined by the polling sequence as shown in table 7-1.

A low-priority interrupt in service can itself be interrupted by a high-priority interrupt, but not by

another low-priority interrupt. A high-priority interrupt in service cannot be interrupted by any other

interrupt source.

The interrupt request flags are located in bit-addressable SFR’s as listed in table 7-2.

Table 7-1

Priority-within-Level Structure

Interrupt Source

Priority

External Interrupt 0,

IE0

Synchronous Serial Channel SSC

Timer 0 Interrupt,

TF0

External Interrupt 1,

IE1

Timer 1 Interrupt,

TF1

Universal Serial Channel,

RI or TI

Timer 2 Interrupt,

TF2 or EXF2

High

↓

Low

Table 7-2

Location of Interrupt Sources Request Flags

Interrupt Request Flag

SFR

Address

Bit-Addr.

External Interrupt 0,

IE0

Timer 0 Interrupt,

TF0

External Interrupt 1,

IE1

Timer 1 Interrupt,

TF1

Universal Serial Channel,

RI (C513/C513A/

C513A-H only)

Universal Serial Channel,

TI (C513/C513A/

C513A-H only)

Timer 2 Interrupt,

TF2

Timer 2 Interrupt,

EXF2

Synchr. Serial Channel

WCOL

TCON

SCON

T2CON

SCF

88H

98H

C8H

F8H

89H

8DH

8BH

8FH

98H

99H

CFH

CEH

F8H

F9H

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