38D2 datasheet(35/136 Pages) RENESAS

35 / 136 page

Rev.3.02

Apr 10, 2008

Page 35 of 131

REJ03B0177-0302

38D2 Group

• Frequency Divider For Timer

Each timer X and timer Y have the frequency dividers for the

count source. The count source of the frequency divider is

switched to XIN, XCIN, or the on-chip oscillator OCO divided by

4 in the on-chip oscillator mode by the CPU mode register. The

division ratio of each timer can be controlled by each timer

division ratio selection bit. The division ratio can be selected

from as follows;

1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(OCO)/4.

Switch the frequency division or count source* while the timer

count is stopped.

*This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

• Timer X

The count source for timer X can be set using the timer X mode

selected, count operation is possible regardless of whether or not

the XIN input oscillator or the on-chip oscillator is operating.

The timer X operates as down-count. When the timer contents

reach “000016”, an underflow occurs at the next count pulse and

the timer latch contents are reloaded. After that, the timer

continues countdown. When the timer underflows, the interrupt

request bit corresponding to the timer X is set to “1”.

Six operating modes can be selected for timer X by the timer X

mode register and timer X control register.

(1) Timer Mode

The count source can be selected by setting the timer X mode

setting the timer X register (extension).

(2) Pulse Output Mode

Pulses of which polarity is inverted each time the timer

underflows are output from the TXOUT1 pin. Except for that, this

mode operates just as in the timer mode.

When using this mode, set the port sharing the TXOUT1 pin to

output mode.

(3) IGBT Output Mode

After dummy output from the TXOUT1 pin, count starts with the

INT0 pin input as a trigger. In the case that the timer X output 1

active edge switch bit is “0”, when the trigger is detected or the

timer X underflows, “H” is output from the TXOUT1 pin. And

then, when the count value corresponds with the compare

After noise is cleared by noise filters, judging continuous 4-time

same levels with sampling clocks to be signals, the INT0 signal

can use 4 types of delay time by a delay circuit.

When using this mode, set the port sharing the INT0 pin to input

mode and set the port sharing the pin used as TXOUT1 or TXOUT2

function to output mode.

When the timer X output control bit 1 or 2 of the timer X control

forcibly by the interrupt signal of INT1 or INT2. And then, the

TXOUT1 output and TXOUT2 output can be set to “L” forcibly at

the same time that the timer X stops counting.

Do not write “1” to the timer X register (extension) when using

the IGBT output mode.

(4) PWM Mode

IGBT dummy output, an external trigger with the INT0 pin and

output control with pins INT1 and INT2 are not used. Except for

those, this mode operates just as in the IGBT output mode.

The period of PWM waveform is specified by the timer X set

value. In the case that the timer X output 1 active edge switch bit

is “0”, the “H” interval is specified by the compare register 1 set

value. In the case that the timer X output 2 active edge switch bit

is “0”, the “H” interval is specified by the compare registers 2

and 3 set values.

When using this mode, set the port sharing the pin used as

TXOUT1 or TXOUT2 function to output mode.

Do not write “1” to the timer X register (extension) when using

the PWM mode.

(5) Event Counter Mode

The timer counts signals input through the CNTR0 pin. In this

mode, timer X operates as the 18-bit counter by setting the timer

X register (extension). When using this mode, set the port

sharing the CNTR0 pin to input mode.

In this mode, the window control can be performed by the timer

1 underflow. When the bit 5 (data for control of event counter

window) of the timer X mode register is set to “1”, counting is

stopped at the next timer 1 underflow. When the bit is set to “0”,

counting is restarted at the next timer 1 underflow.

(6) Pulse Width Measurement Mode

In this mode, the count source is the output of frequency divider

for timer. In this mode, timer X operates as the 18-bit counter by

setting the timer X register (extension). When the bit 6 of the

CNTR0 active edge switch bits is “0”, counting is executed

during the “H” interval of CNTR0 pin input. When the bit is “1”,

counting is executed during the “L” interval of CNTR0 pin input.

When using this mode, set the port sharing the CNTR0 pin to

input mode.

Also, set to enable (“0”) the data for control of event counter

window (bit 5 of timer X mode register (address 002D16)).

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