38D2 datasheet(40/136 Pages) RENESAS

40 / 136 page

Rev.3.02

Apr 10, 2008

Page 40 of 131

REJ03B0177-0302

38D2 Group

SERIAL INTERFACE

• SERIAL I/O

The 38D2 Group has two 8-bit serial I/O (serial I/O1 and serial

I/O2).

Serial I/O can be used as either clock synchronous or

asynchronous (UART) serial I/O. A dedicated timer is also

provided for baud rate generation.

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O mode can be selected by setting the

serial I/O mode selection bit of the serial I/O control register to

“1”.

For clock synchronous serial I/O, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB.

Fig. 31 Block diagram of clock synchronous serial I/O

Fig. 32 Operation of clock synchronous serial I/O function

1/4

F/F

Receive buffer register

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

Shift clock

Serial I/O synchronous

clock selection bit

Baud rate generator

Frequency division ratio 1/(n+1)

BRG count source selection bit

Clock control circuit

Falling-edge detector

Transmit buffer register

Data bus

Shift clock

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Transmit interrupt source selection bit

Data bus

Transmit shift register

Serial I/O control register

Serial I/O status register

Address 001816

[Address 001D16]

Address 001816

[Address 001D16]

Address 001916

[Address 001E16]

Address 001C16

[Address 0FF216]

Address 001A16

[Address 001F16]

P54/RXD1

[P33/RXD2]

P56/SCLK1

[P31/SCLK2]

P57/SRDY1

[P30/SRDY2]

P55/TXD1

[P32/TXD2]

[ ] : For Serial I/O2

φ SOURCE: represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode,

Internal on-chip oscillator divided by 4 in the on-chip

oscillator mode, and Sub clock in the low-speed mode.

φSOURCE

RBF = 1

TSC = 1

TBE = 0

TBE = 1

TSC = 0

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TxD

Serial input RxD

Write pulse to receive/transmit

buffer register

Overrun error (OE)

detection

Notes 1: As the transmit interrupt (TI) source, which can be selected, either when the transmit buffer has emptied (TBE = 1) or

after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data

is output continuously from the TxD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Receive enable signal SRDY

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