38D2 datasheet(48/136 Pages) RENESAS

48 / 136 page

Rev.3.02

Apr 10, 2008

Page 48 of 131

REJ03B0177-0302

38D2 Group

• Bias Control and Applied Voltage to LCD Power Input

Pins

When the voltage is applied from the LCD power input pins

(VL1

−VL3), set the VL pin input selection bit (bit 5 of the LCD

power control register) and VL3 connection bit (bit 6 of LCD

power control register) to “1”, apply the voltage value shown in

Table 12 according to the bias value. In this case, SEG22 pin and

SEG23 pin cannot be used.

Select a bias value by the bias control bit (bit 2 of the LCD mode

Note: VLCD is the maximum value of supplied voltage for the

LCD panel.

• Common Pin and Duty Ratio Control

The common pins (COM0

−COM3) to be used are determined by

duty ratio. Select duty ratio by the duty ratio selection bits (bits 0

and 1 of the LCD mode register). When reset is released, VCC

voltage is output from the common pin.

Note: Unused common pin outputs the unselected waveform.

• Segment Signal Output Pin

The segment signal output pins (SEG0

−SEG23) are shared with

ports P0

−P2. When these pins are used as the segment signal

output pins, set the direction registers of the corresponding pins

to “1”, and set the segment output disable register to “0”.

Also, these pins are set to the input port after reset, the VCC

voltage is output by the pull-up resistor.

Fig. 40 Example of circuit at each bias (at external power input)

Table 12 Bias control and applied voltage to VL1

−VL3

Bias value

Voltage value

1/3 bias

VL3 = VLCD

VL2 = 2/3 VLCD

VL1 = 1/3 VLCD

1/2 bias

VL3 = VLCD

VL2 = VL1 = 1/2 VLCD

Table 13 Duty ratio control and common pins used

Duty

ratio

Duty ratio selection bits

Common pins used

Bit 1

Bit 0

COM0, COM1

COM0

−COM2

COM0

−COM3

R4 = R5

Contrast adjust

1/2 bias

Contrast adjust

R1 = R2 = R3

1/3 bias

VL1

VL3

VL2

VL1

VL3

VL2

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