38D2 datasheet(24/136 Pages) RENESAS

24 / 136 page

Rev.3.02

Apr 10, 2008

Page 24 of 131

REJ03B0177-0302

38D2 Group

INTERRUPTS

The 38D2 Group interrupts are vector interrupts with a fixed

priority scheme, and generated by 16 sources among 18 sources:

6 external, 11 internal, and 1 software.

The interrupt sources, vector addresses(1), and interrupt priority

are shown in Table 10.

Each interrupt except the BRK instruction interrupt has the

interrupt request bit and the interrupt enable bit. These bits and

the interrupt disable flag (I flag) control the acceptance of

interrupt requests. Figure 16 shows an interrupt control diagram.

An interrupt requests is accepted when all of the following

conditions are satisfied:

• Interrupt disable flag ................................ “0”

• Interrupt request bit .................................. “1”

• Interrupt enable bit ................................... “1”

Though the interrupt priority is determined by hardware, priority

processing can be performed by software using the above bits

and flag.

Notes 1:Vector addresses contain interrupt jump destination addresses.

2:Reset function in the same way as an interrupt with the highest priority.

Table 10 Interrupt vector addresses and priority

Interrupt Source

Priority

Vector Addresses(1)

Interrupt Request Generating

Conditions

Remarks

High

Low

Reset (2)

1FFFD16

FFFC16

At reset

Non-maskable

INT0

2FFFB16

FFFA16

At detection of either rising or falling

edge of INT0 input

External interrupt (active edge selectable)

INT1

3FFF916

FFF816

At detection of either rising or falling

edge of INT1 input

External interrupt (active edge selectable)

INT2

4FFF716

FFF616

At detection of either rising or falling

edge of INT2 input

Valid when INT2 interrupt is selected

External interrupt (active edge selectable)

Key input

(key-on wakeup)

At falling of ports P00

−P03, P54−P57

input logical level AND

Valid when key input interrupt is selected

External interrupt (falling valid)

CNTR0

5FFF516

FFF416

At detection of either rising or falling

edge of CNTR0 input

External interrupt (active edge selectable)

Timer X

FFF316

FFF216

At timer X underflow

Timer 1

FFF116

FFF016

At timer 1 underflow

Valid when timer 1 interrupt is selected

Timer 2

FFEF16

FFEE16

At timer 2 underflow

Valid when timer 2 interrupt is selected

Timer 3

FFED16

FFEC16

At timer 3 underflow

Valid when timer 3 interrupt is selected

Timer 4

FFEB16

FFEA16

At timer 4 underflow

Valid when timer 4 interrupt is selected

Serial I/O1 receive

FFE916

FFE816

At completion of serial I/O1 data receive Valid only when serial I/O1 is selected

Serial I/O1 transmit

FFE716

FFE616

At completion of serial I/O1 transmit

shift or transmit buffer is empty

Valid only when serial I/O1 is selected

Serial I/O2 receive

FFE516

FFE416

At completion of serial I/O2 data receive Valid only when serial I/O2 is selected

Serial I/O2 transmit

FFE316

FFE216

At completion of serial I/O2 data

transmit shift or transmit buffer is empty

Valid only when serial I/O2 is selected

Timer Y

FFE116

FFE016

At timer Y underflow

CNTR1

At detection of either rising or falling

edge of CNTR1 input

External interrupt (active edge selectable)

A/D conversion

FFDF16

FFDE16

At completion of A/D conversion

Valid when A/D interrupt is selected

BRK instruction

FFDD16

FFDC16 At BRK instruction execution

Non-maskable software interrupt

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