38D2 datasheet(50/136 Pages) RENESAS

50 / 136 page

Rev.3.02

Apr 10, 2008

Page 50 of 131

REJ03B0177-0302

38D2 Group

• LCD Display RAM

The 12-byte area of address 004016 to 004B16 is the designated

RAM for the LCD display. When “1” is written to these

addresses, the corresponding segments of the LCD display panel

are turned on.

• LCD Drive Timing

For the LCD drive timing, type A or type B can be selected.

The LCD drive timing is selected by the timing selection bit (bit

4 of LCD mode register).

Type A is selected by setting the LCD drive timing selection bit

to “0”, type B is selected by setting the bit to “1”. Type A is

selected after reset.

The LCDCK timing frequency (LCD drive timing) is generated

internally and the frame frequency can be determined with the

following equation;

f(LCDCK) =

Frame frequency =

<Notes>

(1) When the STP instruction is executed, the following bits are

set to “0”;

• LCD enable bit (bit 3 of LCD mode register)

• Bits other than bit 6 of the LCD power control register.

And the LCD panel turns off.

To make the LCD panel turn on after returning from the stop

mode, set these bits to “1”.

(2) When the voltage is applied to VL1 to VL3 by using the

external resistor, write “102” to dividing resistor for LCD

power selection bits (RSEL) of the LCD power control

(3) When the LCD drive control circuit is used at VL3 = VCC,

apply VCC to VL3 pin and write “1” to VL3 connection bit of

the LCD power control register (address 003816).

Fig. 43 LCD display RAM map

(frequency of count source for LCDCK)

(divider division ratio for LCD)

f(LCDCK)

duty ratio

Bit

Address

004016

004116

004216

004316

004416

004516

004616

004716

004816

004916

004A16

004B16

SEG1

SEG3

SEG5

SEG7

SEG9

SEG11

SEG13

SEG15

SEG17

SEG19

SEG21

SEG23

SEG0

SEG2

SEG4

SEG6

SEG8

SEG10

SEG12

SEG14

SEG16

SEG18

SEG20

SEG22

COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0

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