38D2 datasheet(44/136 Pages) RENESAS

44 / 136 page

Rev.3.02

Apr 10, 2008

Page 44 of 131

REJ03B0177-0302

38D2 Group

A/D CONVERTER

The 38D2 Group has a 10-bit A/D converter. The A/D converter

performs successive approximation conversion. The 38D2 Group

has the ADKEY function which perform A/D conversion of the

“L” level analog input from the ADKEY pin automatically.

[AD Conversion Register (ADL, ADH)]

One of these registers is a high-order register, and the other is a

low-order register. The high-order 8 bits of a conversion result is

stored in the AD conversion register (high-order) (address

001716), and the low-order 2 bits of the same result are stored in

bit 7 and bit 6 of the AD conversion register (low-order) (address

001616).

During A/D conversion, do not read these registers.

Also, the connection between the resistor ladder and reference

voltage input pin (VREF) can be controlled by the VREF input

switch bit (bit 0 of address 001616). When “1” is written to this

bit, the resistor ladder is always connected to VREF. When “0” is

written to this bit, the resistor ladder is disconnected from VREF

except during the A/D conversion.

[AD Control Register (ADCON)]

This register controls A/D converter. Bits 2 to 0 are analog input

pin selection bits. Bit 3 is an AD conversion completion bit and

“0” during A/D conversion. This bit is set to “1” upon

completion of A/D conversion.

A/D conversion is started by setting “0” in this bit.

Bit 5 is the ADKEY enable bit. The ADKEY function is enabled

by setting “1” to this bit. When this function is valid, the analog

input pin selection bits are ignored. Also, when bit 5 is “1”, do

not set “0” to bit 3 by program.

[Comparison Voltage Generator]

The comparison voltage generator divides the voltage between

AVSS and VREF, and outputs the divided voltages.

[Channel Selector]

The channel selector selects one of the input ports P47/AN7

−

P40/AN0 and inputs it to the comparator.

[Comparator and Control Circuit]

The comparator and control circuit compare an analog input

voltage with the comparison voltage and store the result in the

AD conversion register. When an A/D conversion is completed,

the control circuit sets the AD conversion completion bit and the

AD conversion interrupt request bit to “1”.

The comparator is constructed linked to a capacitor. The

conversion accuracy may be low because the change is lost if the

conversion speed is not enough.

Accordingly, set f(XIN) to at least 500 kHz during A/D

conversion in the XIN mode.

Also, do not execute the STP and WIT instructions during the

A/D conversion.

In the low-speed mode and on-chip oscillator mode, there is no

limit on the oscillation frequency because the on-chip oscillator

is used as the A/D conversion clock. In the low-speed mode, on-

chip oscillator starts oscillation automatically at the A/D

conversion is executed and stops oscillation automatically at the

A/D conversion is finished even though it is not oscillating.

Fig. 36 Block diagram of A/D converter

(Address 001716)

(Address 001616)

ADKEY

control circuit

A/D control circuit

AVSS

Data bus

AD conversion register (H)

Resistor ladder

Comparator

A/D interrupt request

AD control register

P40/AN0

P41/AN1

P42/AN2/ADKEY

P43/AN3

P44/AN4

P45/AN5

P46/AN6

P47/AN7

AD conversion register (L)

VREF

1/8

1/2

SOURCE

Note: In frequency/2, frequency/4, or frequency/8 mode, φSOURCE is the XIN input.

In low-speed mode, or on-chip oscillator mode, φSOURCE is the on-chip

oscillator frequency divided by 4.

38D2 Datasheet(PDF) 44 Page - Renesas Technology Corp

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