38D2 datasheet(55/136 Pages) RENESAS

55 / 136 page

Rev.3.02

Apr 10, 2008

Page 55 of 131

REJ03B0177-0302

38D2 Group

ROM CORRECTION FUNCTION

A part of program in ROM can be corrected.

Set the start address of the corrected ROM data (i.e. an Op code

address of the beginning instruction) to the ROM correction

address high-order and low-order registers.

When the program is being executed and the value of the

program counter matches with the set address value in the ROM

correction address registers, the program is branched to the ROM

correction vectors and then the correction program can be

executed by setting it to the ROM correction vectors.

Use the JMP instruction (3-byte instruction) to return the main

program from the correction program.

The correctable area is up to two. There are two vectors for ROM

correction.

Also, ROM correction vector can be selected from the RAM area

or ROM area by the ROM correction memory selection bit.

The ROM correction function is controlled by the ROM

correction address 1 enable bit and ROM correction address 2

enable bit.

If the ROM correction function is not used, the ROM correction

vector may be used as normal RAM/ROM. When using the

ROM correction vector as normal RAM/ROM, make sure to set

bits 1 and 0 in the ROM correction enable register to “0”

(Disable).

<Notes>

1. When using the ROM correction function, set the ROM cor-

rection address registers and then enable the ROM correc-

tion with the ROM correction enable register.

2. Do not set addresses other than the ROM area in the ROM

correction address registers.

Do not set the same ROM correction addresses in both the

ROM correction address registers 1 and ROM correction

address registers 2.

3. It is necessary to contain the process for ROM correction in

the program.

Fig. 48 ROM correction address register

Fig. 49 Memory map of M38D24G4

Fig. 50 Structure of ROM correction enable register

RAM area

RC2 = “0”

ROM area

RC2 = “1”

Vector 1

address 010016

address F10016

Vector 2

address 012016

address F12016

0FF816

ROM correction address 1 high-order register (RCA1H)

ROM correction address 1 low-order register (RCA1L)

ROM correction address 2 high-order register (RCA2H)

ROM correction address 2 low-order register (RCA2L)

0FF916

0FFA16

0FFB16

Note: Do not set address other than ROM area.

C08016

SFR area

Interrupt vector area

Reserved ROM area

010016

000016

004016

012016

FF0016

FFFF16

Zero

page

Special

page

02BF16

EFFF16

RAM

ROM

Protect

area 1

F12016

FFDB16

Reserved ROM area

C00016

F10016

ROM correction vector 1

ROM correction vector 2

ROM correction vector 1

ROM correction vector 2

ROM correction address 1 enable bit (RC0)

0 : Disable

1 : Enable

ROM correction address 2 enable bit (RC1)

0 : Disable

1 : Enable

ROM correction memory selection bit (RC2)

0 : Branch to the RAM area

1 : Branch to the ROM area

Not used (returns “0” when read)

ROM correction enable register (Address 0FFC16)

RCR

Note: After ROM correction address register is set,

set the ROM correction address enable bit to be enabled.

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