38D2 datasheet(57/136 Pages) RENESAS

57 / 136 page

Rev.3.02

Apr 10, 2008

Page 57 of 131

REJ03B0177-0302

38D2 Group

CLOCK OUTPUT FUNCTION

A system clock

φ can be output from I/O port P36. The triple

function of I/O port, timer 2 output function and system clock

output function is performed by the clock output control register

(address 0FF316) and the timer 2 output selection bit of the timer

12 mode register (address 002516).

In order to output a system clock

φ from I/O port P36, set the

timer 2 output selection bit and bit 0 of the clock output control

When the clock output function is selected, a clock is output

while the direction register of port P36 is set to the output mode.

P36 is switched to the port output or the output (timer 2 output

and the clock output) except port at the cycle after the timer 2

output control bit is switched.

Fig. 53 Structure of clock output control register

Fig. 54 Block diagram of clock output function

Other function registers

[RRF register (RRFR)]

The RRF register (address 001216) is the 8-bit register and does

not have the control function.

As for the value written in this register, high-order 4 bits and

low-order 4 bits interchange.

It is initialized after reset.

Fig. 55 Structure of RRF register

Clock output control register

(CKOUT : address 0FF316)

P36 clock output control bit

0 : Timer 2 output

1 : System clock

φ output

Not used (returns “0” when read)

Not used (Do not write “1” to these bits.)

Timer 2 latch (8)

Timer 2 (8)

1/2

T2OUT output edge

switch bit

P36 clock output control bit

“0”

“1”

P36 latch

Timer 2 output selection bit

P36 direction register

P36/T2OUT/

CKOUT

Timer 12 mode register (address 002516)

T12M

Timer 2 output selection bit

0 : I/O port

1 : Timer 2 output

System clock

Timer 2 output control bit

“0”

“1”

RRF register

DB4 data storage

DB5 data storage

DB6 data storage

DB7 data storage

DB0 data storage

DB1 data storage

DB2 data storage

DB3 data storage

(RRFR : address 001216)

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