HD64F36022 datasheet(147/384 Pages) RENESAS

147 / 384 page

Section 10 Timer V

Rev. 4.00 Sep. 23, 2005 Page 121 of 354

REJ09B0025-0400

10.3.3

Timer Control Register V0 (TCRV0)

TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,

and controls each interrupt request.

Bit

Bit Name

Initial

Value

R/W

Description

CMIEB

R/W

Compare Match Interrupt Enable B

When this bit is set to 1, interrupt request from the CMFB

bit in TCSRV is enabled.

CMIEA

R/W

Compare Match Interrupt Enable A

When this bit is set to 1, interrupt request from the CMFA

bit in TCSRV is enabled.

OVIE

R/W

Timer Overflow Interrupt Enable

When this bit is set to 1, interrupt request from the OVF

bit in TCSRV is enabled.

CCLR1

CCLR0

R/W

Counter Clear 1 and 0

These bits specify the clearing conditions of TCNTV.

00: Clearing is disabled

01: Cleared by compare match A

10: Cleared by compare match B

11: Cleared on the rising edge of the TMRIV pin. The

operation of TCNTV after clearing depends on TRGE

in TCRV1.

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

These bits select clock signals to input to TCNTV and the

counting condition in combination with ICKS0 in TCRV1.

Refer to table 10.2.

HD64F36022 Datasheet(PDF) 147 Page - Renesas Technology Corp

HD64F36022 Datasheet(HTML) 147 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL