HD64F36022 datasheet(158/384 Pages) RENESAS

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Section 10 Timer V

Rev. 4.00 Sep. 23, 2005 Page 132 of 354

REJ09B0025-0400

10.6

Usage Notes

The following types of contention or operation can occur in timer V operation.

Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear

signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 10.11, clearing

takes precedence and the write to the counter is not carried out. If counting-up is generated in

the T3 state of a TCNTV write cycle, writing takes precedence.

If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write

to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure

10.12 shows the timing.

If compare matches A and B occur simultaneously, any conflict between the output selections

for compare match A and compare match B is resolved by the following priority: toggle

output

> output 1 > output 0.

Depending on the timing, TCNTV may be incremented by a switch between different internal

clock sources. When TCNTV is internally clocked, an increment pulse is generated from the

falling edge of an internal clock signal, that is divided system clock (

φ). Therefore, as shown

in figure 10.3 the switch is from a high clock signal to a low clock signal, the switchover is

seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a

switch between internal and external clocks.

Address

TCNTV address

TCNTV write cycle by CPU

Internal write signal

Counter clear signal

TCNTV

H'00

Figure 10.11 Contention between TCNTV Write and Clear

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