HD64F36022 datasheet(161/384 Pages) RENESAS

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Section 11 Timer W

TIM08W0A_000020020200

Rev. 4.00 Sep. 23, 2005 Page 135 of 354

REJ09B0025-0400

Section 11 Timer W

The timer W has a 16-bit timer having output compare and input capture functions. The timer W

can count external events and output pulses with an arbitrary duty cycle by compare match

between the timer counter and four general registers. Thus, it can be applied to various systems.

11.1

Features

• Selection of five counter clock sources: four internal clocks (φ, φ/2, φ/4, and φ/8) and an

external clock (external events can be counted)

• Capability to process up to four pulse outputs or four pulse inputs

• Four general registers:

 Independently assignable output compare or input capture functions

 Usable as two pairs of registers; one register of each pair operates as a buffer for the output

compare or input capture register

• Four selectable operating modes :

 Waveform output by compare match

Selection of 0 output, 1 output, or toggle output

 Input capture function

Rising edge, falling edge, or both edges

 Counter clearing function

Counters can be cleared by compare match

 PWM mode

Up to three-phase PWM output can be provided with desired duty ratio.

• Any initial timer output value can be set

• Five interrupt sources

Four compare match/input capture interrupts and an overflow interrupt.

Table 11.1 summarizes the timer W functions, and figure 11.1 shows a block diagram of the timer

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