HD64F36022 datasheet(166/384 Pages) RENESAS

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Section 11 Timer W

Rev. 4.00 Sep. 23, 2005 Page 140 of 354

REJ09B0025-0400

11.3.2

Timer Control Register W (TCRW)

TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer

output levels.

Bit

Bit Name

Initial

Value

R/W

Description

CCLR

R/W

Counter Clear

The TCNT value is cleared by compare match A when

this bit is 1. When it is 0, TCNT operates as a free-

running counter.

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

Select the TCNT clock source.

000: Internal clock: counts on

001: Internal clock: counts on

φ/2

010: Internal clock: counts on

φ/4

011: Internal clock: counts on

φ/8

1XX: Counts on rising edges of the external event (FTCI)

When the internal clock source (

φ) is selected, subclock

sources are counted in subactive and subsleep modes.

TOD

R/W

Timer Output Level Setting D

Sets the output value of the FTIOD pin until the first

compare match D is generated.

0: Output value is 0*

1: Output value is 1*

TOC

R/W

Timer Output Level Setting C

Sets the output value of the FTIOC pin until the first

compare match C is generated.

0: Output value is 0*

1: Output value is 1*

TOB

R/W

Timer Output Level Setting B

Sets the output value of the FTIOB pin until the first

compare match B is generated.

0: Output value is 0*

1: Output value is 1*

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