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HD64F36022 Datasheet(PDF) 168 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 168 Page - Renesas Technology Corp |
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168 / 384 page ![]() Section 11 Timer W Rev. 4.00 Sep. 23, 2005 Page 142 of 354 REJ09B0025-0400 11.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVF 0 R/W Timer Overflow Flag [Setting condition] When TCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 to 4 All 1 Reserved These bits are always read as 1. 3 IMFD 0 R/W Input Capture/Compare Match Flag D [Setting conditions] • TCNT = GRD when GRD functions as an output compare register • The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register [Clearing condition] Read IMFD when IMFD = 1, then write 0 in IMFD 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] • TCNT = GRC when GRC functions as an output compare register • The TCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register [Clearing condition] Read IMFC when IMFC = 1, then write 0 in IMFC |
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