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SH7101 Datasheet(PDF) 37 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 37 Page - Renesas Technology Corp |
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37 / 560 page  Section 1 Overview Rev.1.00 Sep. 18, 2008 Page 3 of 522 REJ09B0069-0100 1.2 Internal Block Diagram : Peripheral address bus (12 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVCL PLLCAP PLLVss Vcc VCL VCL Vcc Vcc Vcc Vss Vss Vss Vss AVcc AVcc AVss AVss Serial communication interface (x 2 channels) Multifunction timer pulse unit Interrupt controller Bus state controller Compare match timer (x 2 channels) A/D converter Watchdog timer Masked ROM 256 kbytes/128 kbytes/ 64 kbytes/32 kbytes CPU RAM 8 kbytes/4 kbytes/ 2 kbytes Motor management timer (x 1 channel) Figure 1.1 Internal Block Diagram of SH7108/SH7106/SH7104/SH7101 |
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