SH7101 datasheet(60/560 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Sep. 18, 2008 Page 26 of 522

REJ09B0069-0100

2.4.3

Instruction Format

The instruction formats and the meaning of source and destination operand are described below.

The meaning of the operand depends on the instruction code. The symbols used are as follows:

• xxxx: Instruction code

• mmmm: Source register

• nnnn: Destination register

• iiii: Immediate data

• dddd: Displacement

Table 2.9

Instruction Formats

Source

Operand

Destination

Operand

Example

0 format

xxxx

—

NOP

—

nnnn: Direct

MOVT

Control register or

system register

nnnn: Direct

STS

MACH,Rn

n format

xxxx

nnnn

Control register or

system register

nnnn: Indirect pre-

decrement register

STC.L SR,@-Rn

mmmm: Direct

Control register or

system register

LDC

Rm,SR

mmmm: Indirect

post-increment

Control register or

system register

LDC.L @Rm+,SR

mmmm: Indirect

—

JMP

@Rm

m format

xxxx

mmmm

xxxx

mmmm: PC

relative using Rm

—

BRAF

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