SH7101 datasheet(63/560 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Sep. 18, 2008 Page 29 of 522

REJ09B0069-0100

Table 2.10

Classification of Instructions

Classification Types

Operation

Code

Function

No. of

Instructions

MOV

Data transfer, immediate data transfer,

peripheral module data transfer, structure data

transfer

MOVA

Effective address transfer

MOVT

T bit transfer

SWAP

Swap of upper and lower bytes

Data transfer

XTRCT

Extraction of the middle of registers connected

ADD

Binary addition

ADDC

Binary addition with carry

ADDV

Binary addition with overflow check

CMP/cond Comparison

DIV1

Division

Arithmetic

operations

DIV0S

Initialization of signed division

DIV0U

Initialization of unsigned division

DMULS

Signed double-length multiplication

DMULU

Unsigned double-length multiplication

Decrement and test

EXTS

Sign extension

EXTU

Zero extension

MAC

Multiply-and-accumulate, double-length

multiply-and-accumulate operation

MUL

Double-length multiply operation

MULS

Signed multiplication

MULU

Unsigned multiplication

NEG

Negation

NEGC

Negation with borrow

SUB

Binary subtraction

SUBC

Binary subtraction with borrow

SUBV

Binary subtraction with underflow

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