SH7101 datasheet(93/560 Pages) RENESAS

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Section 5 Exception Processing

Rev.1.00 Sep. 18, 2008 Page 59 of 522

REJ09B0069-0100

Section 5 Exception Processing

5.1

Overview

5.1.1

Types of Exception Processing and Priority

Exception processing is started by four sources: resets, address errors, interrupts and instructions

and have the priority, as shown in table 5.1. When several exception processing sources occur at

once, they are processed according to the priority.

Table 5.1

Types of Exception Processing and Priority

Exception

Source

Priority

Reset

Power-on reset

High

Manual reset

Address

error

CPU address error

Interrupt

NMI

IRQ

On-chip peripheral

modules:

• Multifunction timer pulse unit (MTU)

• A/D converter 0 and 1 (A/D0, A/D1)

• Compare match timer 0 and 1 (CMT0, CMT1)

• Watchdog timer (WDT)

• Input/output port (I/O) (MTU)

• Serial communication interface 2 and 3 (SCI2 and

SCI3)

• Motor management timer (MMT)

• A/D converter 2 (A/D2)

• Input/output port (I/O) (MMT)

Instructions

Trap instruction (TRAPA instruction)

General illegal instructions (undefined code)

Illegal slot instructions (undefined code placed directly after a delay

branch instruction*

1 or instructions that rewrite the PC*2)

Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and

BRAF.

2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, and BRAF.

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