SH7101 datasheet(59/560 Pages) RENESAS

59 / 560 page

Section 2 CPU

Rev.1.00 Sep. 18, 2008 Page 25 of 522

REJ09B0069-0100

Addressing

Mode

Instruction

Format

Effective Address Calculation

Equation

PC relative

addressing

disp:8

The effective address is the sum of PC value and

the value that is obtained by doubling the sign-

extended 8-bit displacement (disp).

disp

(sign-extended)

PC + disp

× 2

PC + disp

× 2

disp:12

The effective address is the sum of PC value and

the value that is obtained by doubling the sign-

extended 12-bit displacement (disp).

disp

(sign-extended)

PC + disp

× 2

PC + disp

× 2

The effective address is the sum of the register PC

and Rn.

PC + Rn

Immediate

addressing

#imm:8

The 8-bit immediate data (imm) for the TST, AND,

OR, and XOR instructions is zero-extended.

—

#imm:8

The 8-bit immediate data (imm) for the MOV, ADD,

and CMP/EQ instructions is sign-extended.

—

#imm:8

The 8-bit immediate data (imm) for the TRAPA

instruction is zero-extended and then quadrupled.

—

SH7101 Datasheet(PDF) 59 Page - Renesas Technology Corp

SH7101 Datasheet(HTML) 59 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL