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SH7101 Datasheet(PDF) 38 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 38 Page - Renesas Technology Corp |
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38 / 560 page  Section 1 Overview Rev.1.00 Sep. 18, 2008 Page 4 of 522 REJ09B0069-0100 : Peripheral address bus (12 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) RES WDTOVF HSTBY MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVCL PLLCAP PLLVss VCL VCL Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss AVcc AVcc AVss AVss Serial communication interface (x 2 channels) Multifunction timer pulse unit Interrupt controller Bus state controller Compare match timer (x 2 channels) A/D converter Watchdog timer Masked ROM 256 kbytes/ 128 kbytes/64 kbytes CPU RAM 8 kbytes/4 kbytes P L L PD8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2/SCK2 PD1/D1/TxD2 PD0/D0/RxD2 Motor management timer (x 1 channel) Figure 1.2 Internal Block Diagram of SH7109/SH7107/SH7105 |
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